HD64336900G Datasheet, PDF (254/408 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

SCL
Output
control
Noise canceler
SDA
Output
control
Transmit/
receive
control circuit
ICDRT
ICDRS
Transfer clock
generation
circuit
ICCR1
ICCR2
ICMR
SAR
Noise canceler
ICDRR
Address
comparator
Bus state
decision circuit
Arbitration
decision circuit
[Legend]
ICCR1: I²C bus control register 1
ICCR2: I²C bus control register 2
ICMR: I²C bus mode register
ICSR: I²C bus status register
ICIER: I²C bus interrupt enable register
ICDRT: I²C bus transmit data register
ICDRR: I²C bus receive data register
ICDRS: I²C bus shift register
SAR: Slave address register
ICIER
ICSR
Interrupt
generator
Figure 15.1 Block Diagram of I²C Bus Interface 2
Interrupt request
Rev. 1.00, 11/03, page 226 of 376