HD64336900G Datasheet, PDF (78/408 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

3.2.5 Interrupt Flag Register 1 (IRR1)
IRR1 is a status flag register for direct transition interrupts, and IRQ3 and IRQ0 interrupt requests.
Initial
Bit
Bit Name Value R/W Description
7
IRRDT 0
R/W Direct Transfer Interrupt Request Flag
[Setting condition]
When a direct transfer is made by executing a SLEEP
instruction while DTON in SYSCR2 is set to 1.
[Clearing condition]
When IRRDT is cleared by writing 0
6

0

Reserved
This bit is always read as 0.
5, 4 
All 1

Reserved
These bits are always read as 1.
3
IRRI3
0
R/W IRQ3 Interrupt Request Flag
[Setting condition]
When IRQ3 pin is designated for interrupt input and the
designated signal edge is detected
[Clearing condition]
When IRRI3 is cleared by writing 0
2, 1 
All 0

Reserved
These bits are always read as 0.
0
IRRl0
0
R/W IRQ0 Interrupt Request Flag
[Setting condition]
When IRQ0 pin is designated for interrupt input and the
designated signal edge is detected
[Clearing condition]
When IRRI0 is cleared by writing 0
Rev. 1.00, 11/03, page 50 of 376