HD64336900G Datasheet, PDF (256/408 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

15.3.1 I²C Bus Control Register 1 (ICCR1)
ICCR1 enables or disables the I²C bus interface 2, controls transmission or reception, and selects
master or slave mode, transmission or reception, and transfer clock frequency in master mode.
Bit Bit Name Initial Value R/W
7
ICE
0
R/W
6
RCVD 0
R/W
5
MST
0
R/W
4
TRS
0
R/W
3 to 0 CKS3 to All 0
R/W
CKS0
Description
I²C Bus Interface Enable
0: This module is halted. (SCL and SDA pins are set to
port function.)
1: This bit is enabled for transfer operations. (SCL and
SDA pins are bus drive state.)
Reception Disable
This bit enables or disables the next operation when TRS
is 0 and ICDRR is read.
0: Enables next reception
1: Disables next reception
Master/Slave Select
Transmit/Receive Select
In master mode with the I²C bus format, when arbitration is
lost, MST and TRS are both reset by hardware, causing a
transition to slave receive mode. Modification of the TRS
bit should be made between transfer frames.
After data receive has been started in slave receive mode,
when the first seven bits of the receive data agree with the
slave address that is set to SAR and the eighth bit is 1,
TRS is automatically set to 1. If an overrun error occurs in
master mode with the clock synchronous serial format,
MST is cleared to 0 and slave receive mode is entered.
Operating modes are described below according to MST
and TRS combination. When clocked synchronous serial
format is selected and MST is 1, clock is output.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Transfer Clock Select 3 to 0
These bits should be set according to the necessary
transfer rate in master mode. In slave mode, these bits are
used reservation of the set up time in transmit mode. The
time is 10Tcyc when CKS3 = 0, and 20Tcyc when CKS3 = 1.
(see table 15.2)
Rev. 1.00, 11/03, page 228 of 376