HD64336900G Datasheet, PDF (260/408 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Bit Bit Name Initial Value R/W Description
2 BC2
0
R/W Bit Counter 2 to 0
1 BC1
0
0 BC0
0
R/W These bits specify the number of bits to be transferred next.
R/W
When read, the remaining number of transfer bits is
indicated. With the I²C bus format, the data is transferred
with one addition acknowledge bit. Bit BC2 to BC0 settings
should be made during an interval between transfer frames.
If bits BC2 to BC0 are set to a value other than 000, the
setting should be made while the SCL pin is low. The value
returns to 000 at the end of a data transfer, including the
acknowledge bit. With the clock synchronous serial format,
these bits should not be modified.
I²C Bus Format
Clock Synchronous Serial Format
000: 9 bits
000: 8 bits
001: 2 bits
001: 1 bits
010: 3 bits
010: 2 bits
011: 4 bits
011: 3 bits
100: 5 bits
100: 4 bits
101: 6 bits
101: 5 bits
110: 7 bits
110: 6 bits
111: 8 bits
111: 7 bits
15.3.4 I²C Bus Interrupt Enable Register (ICIER)
ICIER enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be
transferred, and confirms acknowledge bits to be received.
Bit Bit Name Initial Value R/W Description
7 TIE
0
R/W Transmit Interrupt Enable
When the TDRE bit in ICSR is set to 1, this bit enables or
disables the transmit data empty interrupt (TXI).
0: Transmit data empty interrupt request (TXI) is disabled.
1: Transmit data empty interrupt request (TXI) is enabled.
6 TEIE
0
R/W Transmit End Interrupt Enable
This bit enables or disables the transmit end interrupt (TEI) at
the rising of the ninth clock while the TDRE bit in ICSR is 1.
TEI can be canceled by clearing the TEND bit or the TEIE bit
to 0.
0: Transmit end interrupt request (TEI) is disabled.
1: Transmit end interrupt request (TEI) is enabled.
Rev. 1.00, 11/03, page 232 of 376