HD64336900G Datasheet, PDF (257/408 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Table 15.2 Transfer Rate
Bit 3
CKS3
0
Bit 2
CKS2
0
Bit 1
CKS1
0
1
1
0
1
1
0
0
1
1
0
1
Bit 0
CKS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Clock
φ/28
φ/40
φ/48
φ/64
φ/80
φ/100
φ/112
φ/128
φ/56
φ/80
φ/96
φ/128
φ/160
φ/200
φ/224
φ/256
φ = 5 MHz
179 kHz
125 kHz
104 kHz
78.1 kHz
62.5 kHz
50.0 kHz
44.6 kHz
39.1 kHz
89.3 kHz
62.5 kHz
52.1 kHz
39.1 kHz
31.3 kHz
25.0 kHz
22.3 kHz
19.5 kHz
Transfer Rate
φ = 8 MHz φ = 10 MHz
286 kHz
357 kHz
200 kHz
250 kHz
167 kHz
208 kHz
125 kHz
156 kHz
100 kHz
125 kHz
80.0 kHz
100 kHz
71.4 kHz
89.3 kHz
62.5 kHz
78.1 kHz
143 kHz
179 kHz
100 kHz
125 kHz
83.3 kHz
104 kHz
62.5 kHz
78.1 kHz
50.0 kHz
62.5 kHz
40.0 kHz
50.0 kHz
35.7 kHz
44.6 kHz
31.3 kHz
39.1 kHz
15.3.2 I²C Bus Control Register 2 (ICCR2)
ICCR2 issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls
reset in the control part of the I²C bus interface 2.
Bit Bit Name Initial Value R/W Description
7 BBSY
0
R/W Bus Busy
This bit enables to confirm whether the I²C bus is occupied
or released and to issue start/stop conditions in master
mode. With the clocked synchronous serial format, this bit
has no meaning. With the I²C bus format, this bit is set to 1
when the SDA level changes from high to low under the
condition of SCL = high, assuming that the start condition
has been issued. This bit is cleared to 0 when the SDA level
changes from low to high under the condition of SCL = high,
assuming that the stop condition has been issued. Write 1 to
BBSY and 0 to SCP to issue a start condition. Follow this
procedure when also re-transmitting a start condition. Write 0
in BBSY and 0 in SCP to issue a stop condition. To issue
start/stop conditions, use the MOV instruction.
Rev. 1.00, 11/03, page 229 of 376