HD64336900G Datasheet, PDF (118/408 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Table 6.3 Internal State in Each Operating Mode
Function
System clock oscillator
CPU
Instructions
operations _Registers
RAM
IO ports
Active Mode
Functioning
Functioning
Functioning
Functioning
Functioning
External IRQ3, IRQ0
interrupts _WKP5
Peripheral Timer B1
modules _{Timer V}
Timer W
Watchdog
timer
Functioning
Functioning
Functioning
Functioning
Functioning
Functioning
SCI3
IIC2
A/D converter
LVD
Functioning
Functioning
Functioning
Functioning
Sleep Mode
Functioning
Halted
Retained
Retained
Retained
Functioning
Functioning
Functioning
Functioning
Functioning
Functioning
Functioning
Functioning
Functioning
Functioning
Subsleep Mode Standby Mode
Halted
Halted
Halted
Halted
Retained
Retained
Retained
Retained
Retained
Register contents are
retained, but output is the
high-impedance state.
Functioning
Functioning
Functioning
Functioning
Retained
Retained
Reset
Reset
Retained
Retained
Retained
(Functioning if the internal oscillator is selected
as a count clock.)
Reset
Reset
Retained
Retained
Reset
Reset
Functioning
Functioning
6.2.1 Sleep Mode
In sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock
frequency set by the MA2 to MA0 bits in SYSCR2. CPU register contents are retained. When an
interrupt is requested, sleep mode is cleared and the CPU starts interrupt exception handling. Sleep
mode is not cleared if the I bit in the condition code register (CCR) is set to 1 or the requested
interrupt is disabled by the interrupt enable bit. When the RES pin is driven low in sleep mode, the
CPU goes into the reset state and sleep mode is cleared.
Rev. 1.00, 11/03, page 90 of 376