HD64336900G Datasheet, PDF (21/408 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Figure 11.10 Example of Pulse Output Synchronized to TRGV Input.......................................148
Figure 11.11 Contention between TCNTV Write and Clear ......................................................149
Figure 11.12 Contention between TCORA Write and Compare Match .....................................150
Figure 11.13 Internal Clock Switching and TCNTV Operation .................................................150
Section 12 Timer W
Figure 12.1 Timer W Block Diagram .........................................................................................153
Figure 12.2 Free-Running Counter Operation ............................................................................164
Figure 12.3 Periodic Counter Operation .....................................................................................165
Figure 12.4 0 and 1 Output Example (TOA = 0, TOB = 1) ........................................................165
Figure 12.5 Toggle Output Example (TOA = 0, TOB = 1) ........................................................166
Figure 12.6 Toggle Output Example (TOA = 0, TOB = 1) ........................................................166
Figure 12.7 Input Capture Operating Example ...........................................................................167
Figure 12.8 Buffer Operation Example (Input Capture) .............................................................167
Figure 12.9 PWM Mode Example (1) ........................................................................................168
Figure 12.10 PWM Mode Example (2) ......................................................................................169
Figure 12.11 Buffer Operation Example (Output Compare) ......................................................169
Figure 12.12 PWM Mode Example (TOB, TOC, and TOD = 0: Initial Output Values are
Set to 0) .................................................................................................................170
Figure 12.13 PWM Mode Example (TOB, TOC, and TOD = 1: Initial Output Values are
Set to 1) .................................................................................................................171
Figure 12.14 Count Timing for Internal Clock Source ...............................................................172
Figure 12.15 Count Timing for External Clock Source ..............................................................172
Figure 12.16 Output Compare Output Timing............................................................................173
Figure 12.17 Input Capture Input Signal Timing........................................................................174
Figure 12.18 Timing of Counter Clearing by Compare Match...................................................174
Figure 12.19 Buffer Operation Timing (Compare Match)..........................................................175
Figure 12.20 Buffer Operation Timing (Input Capture) .............................................................175
Figure 12.21 Timing of IMFA to IMFD Flag Setting at Compare Match ..................................176
Figure 12.22 Timing of IMFA to IMFD Flag Setting at Input Capture ......................................177
Figure 12.23 Timing of Status Flag Clearing by CPU................................................................177
Figure 12.24 Contention between TCNT Write and Clear .........................................................179
Figure 12.25 Internal Clock Switching and TCNT Operation ....................................................179
Figure 12.26 When Compare Match and Bit Manipulation Instruction to TCRW Occur
at the Same Timing................................................................................................180
Section 13 Watchdog Timer
Figure 13.1 Block Diagram of Watchdog Timer ........................................................................181
Figure 13.2 Watchdog Timer Operation Example ......................................................................185
Section 14 Serial Communication Interface 3 (SCI3)
Figure 14.1 Block Diagram of SCI3 ...........................................................................................188
Figure 14.2 Block Diagram of Noise Filter Circuit ....................................................................201
Figure 14.3 Data Format in Asynchronous Communication ......................................................202
Rev. 1.00, 11/03, page xxi of xxviii