HD64336900G Datasheet, PDF (132/408 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Write pulse application subroutine
Apply Write Pulse
WDT enable
Set PSU bit in FLMCR1
Wait 50 µs
Set P bit in FLMCR1
Wait (Wait time = Programming time)
Clear P bit in FLMCR1
Wait 5 µs
Clear PSU bit in FLMCR1
Wait 5 µs
Disable WDT
End Sub
START
Disable WDT
*2
Set SWE bit in FLMCR1
Wait 1 µs
*1
Store 64-byte program data in program
data area and reprogram data area
n=1
m= 0
Write 64-byte data in RAM reprogram
data area consecutively to flash memory
Apply Write pulse
Set PV bit in FLMCR1
Wait 4 µs
Set block start address as
verify address
Increment address
H'FF dummy write to verify address
Wait 2 µs
*1
Read verify data
Verify data =
No
Write data?
Yes
No
n≤6?
Yes
Additional-programming data computation
m=1
Reprogram data computation
n←n+1
64-byte
No
data verification completed?
Yes
Clear PV bit in FLMCR1
Wait 2 µs
No
n ≤ 6?
Yes
Successively write 64-byte data from additional-
programming data area in RAM to flash memory
Sub-Routine-Call
Apply Write Pulse
No
m=0?
Yes
Clear SWE bit in FLMCR1
Wait 100 µs
End of programming
Yes
n ≤ 1000 ?
No
Clear SWE bit in FLMCR1
Wait 100 µs
Programming failure
Notes: 1. The RTS instruction must not be used during the following (1) and (2) periods.
(1) A period between 64-byte data programming to flash memory and the P bit clearing
(2) A period between dummy writing of H'FF to a verify address and verify data reading
2. When WDT is in use, disable it once.
Figure 7.3 Program/Program-Verify Flowchart
Rev. 1.00, 11/03, page 104 of 376