HD64336900G Datasheet, PDF (298/408 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Bit
7
6
5
4
3
2
1
0
Note:
Initial
Bit Name Value R/W Description
LVDE
1*
R/W LVD Enable
0: Low-voltage detection circuit is not used (standby
mode)
1: Low-voltage detection circuit is used
BGRE
1*
R/W BGR Enable
0: BGR circuit is not used (standby mode)
1: BGR circuit is used
VDDII
1*
R/W LVDR External Compared Voltage Input Inhibit
0: Use external voltage as LVDI compared voltage
1: Use internal voltage as LVDI compared voltage

1

Reserved
This bit is always read as 1 and cannot be modified.
LVDSEL 0*
R/W LVDR Detection Level Select
0: Reset detection voltage is 2.3 V (Typ.)
1: Reset detection voltage is 3.6 V (Typ.)
When the falling or rising voltage detection interrupt is
used, the reset detection voltage of 2.3 V (Typ.) should
be used. When only a reset detection interrupt is used,
reset detection voltage of 3.6 V (Typ.) should be used.
LVDRE 1*
R/W LVDR Enable
0: Disables an LVDR
1: Enables an LVDR
LVDDE 0
R/W Voltage-Fall-Interrupt Enable
0: Interrupt on the power-supply voltage falling disabled
1: Interrupt on the power-supply voltage falling enabled
LVDUE 0
R/W Voltage-Rise-Interrupt Enable
0: Interrupt on the power-supply voltage rising disabled
1: Interrupt on the power-supply voltage rising enabled
* Not initialized by an LVDR but initialized by a power-on reset or a watchdog timer reset.
Rev. 1.00, 11/03, page 270 of 376