HD64336900G Datasheet, PDF (215/408 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 14 Serial Communication Interface 3 (SCI3)
This LSI includes serial communication interface 3 (SCI3). SCI3 can handle both asynchronous
and clocked synchronous serial communication. In asynchronous mode, serial data communication
can be carried out using standard asynchronous communication chips such as a Universal
Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface
Adapter (ACIA). A function is also provided for serial communication between processors
(multiprocessor communication function).
Figure 14.1 is a block diagram of SCI3.
14.1 Features
• Choice of asynchronous or clocked synchronous serial communication mode
• Full-duplex communication capability
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed simultaneously.
Double-buffering is used in both the transmitter and the receiver, enabling continuous
transmission and continuous reception of serial data.
• On-chip baud rate generator allows any bit rate to be selected
• External clock or on-chip baud rate generator can be selected as a transfer clock source.
• Six interrupt sources
Transmit-end, transmit-data-empty, receive-data-full, overrun error, framing error, and parity
error.
• Internal noise filter circuit (available for asynchronous serial communication only)
Asynchronous mode
• Data length: 7 or 8 bits
• Stop bit length: 1 or 2 bits
• Parity: Even, odd, or none
• Receive error detection: Parity, overrun, and framing errors
• Break detection: Break can be detected by reading the RXD pin level directly in the case of a
framing error
Clocked synchronous mode
• Data length: 8 bits
• Receive error detection: Overrun errors
SCI0010A_000120030300
Rev. 1.00, 11/03, page 187 of 376