HD64336900G Datasheet, PDF (259/408 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

15.3.3 I²C Bus Mode Register (ICMR)
ICMR selects whether the MSB or LSB is transferred first, performs master mode wait control,
and selects the transfer bit count.
Bit Bit Name
7 MLS
6 WAIT
5, 4 
3 BCWP
Initial Value R/W Description
0
R/W MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
Set this bit to 0 when the I²C bus format is used.
0
R/W Wait Insertion Bit
In master mode with the I²C bus format, this bit selects
whether to insert a wait after data transfer except the
acknowledge bit. When WAIT is set to 1, after the fall of the
clock for the final data bit, low period is extended for two
transfer clocks. If WAIT is cleared to 0, data and
acknowledge bits are transferred consecutively with no wait
inserted.
The setting of this bit is invalid in slave mode with the I²C bus
format or with the clocked synchronous serial format.
All 1
 Reserved
These bits are always read as 1.
1
R/W BC Write Protect
This bit controls the BC2 to BC0 modifications. When
modifying BC2 to BC0, this bit should be cleared to 0 and
use the MOV instruction. In clock synchronous serial mode,
BC should not be modified.
0: When writing, values of BC2 to BC0 are set.
1: When reading, 1 is always read.
When writing, settings of BC2 to BC0 are invalid.
Rev. 1.00, 11/03, page 231 of 376