HD64336900G Datasheet, PDF (105/408 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

φOSC
φRC
φ
External clock halt
OSCHLT
PHISTOP
(Internal signal)
CKSTA
CKSWIF
External RC clock operation
φ_OSC halt
detected*¹
φ halt*²
Internal clock
operation
T_chk
[Legend]
φOSC:
φRC:
φ:
OSCHLT:
External clock
Internal RC clock
System clock
Bit 1 in CKCSR
PHISTOP: System clock stop control signal
CKSTA: Bit 0 in CKCSR
CKSWIF: Bit 2 in CKCSR
Notes: 1. 44 × φ_RC ≤ T_chk ≤ 48 × φ_RC
2. The φ halt duration is the duration from the timing when the φ clock stops to the
seventh rising edge of the φ_RC clock.
Figure 5.8 External Oscillation Backup Timing
Rev. 1.00, 11/03, page 77 of 376