HD64336900G Datasheet, PDF (301/408 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

17.3.2 Low-Voltage Detection Circuit
LVDR (Reset by Low Voltage Detection) Circuit:
Figure 17.4 shows the timing of the operation of the LVDR circuit. The LVDR circuit is enabled
after a power-on reset is released. To cancel the LVDR circuit, first the LVDRE bit in LVDCR
should be cleared to 0 and then the LVDE bit in LVDCR and, if necessary, the BGRE bit should
be cleared to 0. The LVDE and the BGRE bits must not be cleared to 0 simultaneously with the
LVDRE bit because incorrect operation may occur. To restart the LVDR circuit, set the LVDE bit
and the BGRE bit to 1, wait for 50 µs (t_LVDON) given by a software timer until the reference
voltage and the low-voltage-detection power supply have settled, then set the LVDRE bit to 1.
After that, the output settings of ports must be made.
When the power-supply voltage falls below the Vreset voltage (2.3 V or 3.6 V (Typ.)), the LVDR
circuit clears the LVDRES signal to 0, and resets prescaler S. The low-voltage detection reset state
remains in place until a power-on reset is generated. When the power-supply voltage rises above
the Vreset voltage again, prescaler S starts counting. It counts 131,072 clock (φ) cycles, and then
releases the internal reset signal. In this case, the LVDE, BGRE, VDDII, LVDSEL, and LVDRE
bits in LVDCR are not initialized.
Note that if the power supply voltage (Vcc) falls below V_LVDRmin = 1.0 V and then rises from that
point, the low-voltage detection reset may not occur.
If the power supply voltage (Vcc) falls below Vpor = 100 mV, a power-on reset occurs.
VCC
VLVDRmin
Vreset
VSS
PSS-reset
signal
OVF
Internal reset
signal
131,072 cycles
PSS counter starts
Reset released
Figure 17.4 Operating Timing of LVDR Circuit
Rev. 1.00, 11/03, page 273 of 376