HD64336900G Datasheet, PDF (276/408 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

SCL
SDA
(Input)
MST
1
2
Bit 0 Bit 1
7
8
1
Bit 6 Bit 7 Bit 0
7
8
1
2
Bit 6 Bit 7
Bit 0
TRS
RDRF
ICDRS
Data 1
Data 2
Data 3
ICDRR
Data 1
User
processing ^{[2] Set MST}
(when outputting the clock)
[3] Read ICDRR
Figure 15.15 Receive Mode Operation Timing
Data 2
[3] Read ICDRR
15.4.7 Noise Canceler
The logic levels at the SCL and SDA pins are routed through the noise canceler before being
latched internally. Figure 15.16 shows a block diagram of the noise canceler.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
Sampling clock
SCL or SDA
input signal
C
D
Q
Latch
C
D
Q
Latch
March detector
Internal
SCL or SDA
signal
Sampling
clock
System clock
period
Figure 15.16 Block Diagram of Noise Canceler
Rev. 1.00, 11/03, page 248 of 376