HD64336900G Datasheet, PDF (103/408 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

5.3.2 Clock Change Timing
The timing for changing clocks are shown in figures 5.6 to 5.8.
φOSC
φRC
φ
OSCSEL
PHISTOP
(Internal signal)
CKSTA
Internal RC clock operation
φ halt*
External clock operation
Wait for external
oscillation settling
Nwait
[Legend]
φOSC: External clock
φRC:
Internal RC clock
φ:
System clock
OSCSEL: Bit 4 in CKCSR
PHISTOP: System clock stop control signal
CKSTA: Bit 0 in CKCSR
Note: * The φ halt duration is the duration from the timing when the φ clock stops to the first
rising edge of the φ_OSC clock after seven clock cycles of the φ_RC clock have elapsed.
Figure 5.6 Timing Chart of Switching Internal RC Clock to External Clock
Rev. 1.00, 11/03, page 75 of 376