HD64336900G Datasheet, PDF (270/408 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Master transmit mode
SCL
(Master output)
9
SDA
(Master output)
SDA
(Slave output)
A
TDRE
Master receive mode
1
2
3
4
5
6
7
8
9
1
A
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7
TEND
TRS
RDRF
ICDRS
Data 1
ICDRR
Data 1
User
processing
[1] Clear TDRE after clearing [2] Read ICDRR (dummy read)
TEND and TRS
[3] Read ICDRR
Figure 15.7 Master Receive Mode Operation Timing (1)
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
RDRF
9
1
2
3
4
5
6
7
8
9
A
A/
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RCVD
ICDRS Data n-1
Data n
ICDRR
Data n-1
Data n
User
processing
[5] Read ICDRR after setting RCVD
[7] Read ICDRR,
and clear RCVD
[6] Issue stop
condition _{[8] Set slave}
receive mode
Figure 15.8 Master Receive Mode Operation Timing (2)
Rev. 1.00, 11/03, page 242 of 376