HD64336900G Datasheet, PDF (14/408 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Section 14 Serial Communication Interface 3 (SCI3) .......................................187
14.1 Features ............................................................................................................................. 187
14.2 Input/Output Pins .............................................................................................................. 189
14.3 Register Descriptions ........................................................................................................ 189
14.3.1 Receive Shift Register (RSR) .............................................................................. 190
14.3.2 Receive Data Register (RDR) .............................................................................. 190
14.3.3 Transmit Shift Register (TSR) ............................................................................. 190
14.3.4 Transmit Data Register (TDR)............................................................................. 190
14.3.5 Serial Mode Register (SMR)................................................................................ 191
14.3.6 Serial Control Register 3 (SCR3)......................................................................... 192
14.3.7 Serial Status Register (SSR) ................................................................................ 194
14.3.8 Bit Rate Register (BRR) ...................................................................................... 196
14.3.9 Sampling Mode Register (SPMR) ....................................................................... 201
14.4 Operation in Asynchronous Mode .................................................................................... 202
14.4.1 Clock.................................................................................................................... 202
14.4.2 SCI3 Initialization................................................................................................ 203
14.4.3 Data Transmission ............................................................................................... 204
14.4.4 Serial Data Reception .......................................................................................... 206
14.5 Operation in Clocked Synchronous Mode ........................................................................ 208
14.5.1 Clock.................................................................................................................... 208
14.5.2 SCI3 Initialization................................................................................................ 208
14.5.3 Serial Data Transmission ..................................................................................... 209
14.5.4 Serial Data Reception (Clocked Synchronous Mode).......................................... 211
14.5.5 Simultaneous Serial Data Transmission and Reception....................................... 213
14.6 Multiprocessor Communication Function......................................................................... 215
14.6.1 Multiprocessor Serial Data Transmission ............................................................ 217
14.6.2 Multiprocessor Serial Data Reception ................................................................. 218
14.7 Interrupts ........................................................................................................................... 222
14.8 Usage Notes ...................................................................................................................... 223
14.8.1 Break Detection and Processing .......................................................................... 223
14.8.2 Mark State and Break Sending............................................................................. 223
14.8.3 Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only) .................................................................... 223
14.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous
Mode.................................................................................................................... 224
Section 15 I²C Bus Interface 2 (IIC2) ...............................................................225
15.1 Features ............................................................................................................................. 225
15.2 Input/Output Pins .............................................................................................................. 227
15.3 Register Descriptions ........................................................................................................ 227
15.3.1 I²C Bus Control Register 1 (ICCR1).................................................................... 228
15.3.2 I²C Bus Control Register 2 (ICCR2).................................................................... 229
15.3.3 I²C Bus Mode Register (ICMR)........................................................................... 231
Rev. 1.00, 11/03, page xiv of xxviii