HD64336900G Datasheet, PDF (22/408 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Figure 14.4 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode)(Example with 8-Bit Data, Parity, Two Stop Bits) .............. 202
Figure 14.5 Sample SCI3 Initialization Flowchart ..................................................................... 203
Figure 14.6 Example of SCI3 Transmission in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit) ........................................................................... 204
Figure 14.7 Sample Serial Transmission Data Flowchart (Asynchronous Mode)...................... 205
Figure 14.8 Example of SCI3 Reception in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit) ........................................................................... 206
Figure 14.9 Sample Serial Reception Data Flowchart (Asynchronous Mode) ........................... 207
Figure 14.10 Data Format in Clocked Synchronous Communication ........................................ 208
Figure 14.11 Example of SCI3 Transmission in Clocked Synchronous Mode........................... 209
Figure 14.12 Sample Serial Transmission Flowchart (Clocked Synchronous Mode) ................ 210
Figure 14.13 Example of SCI3 Reception in Clocked Synchronous Mode................................ 211
Figure 14.14 Sample Serial Reception Flowchart (Clocked Synchronous Mode)...................... 212
Figure 14.15 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
(Clocked Synchronous Mode) ............................................................................... 214
Figure 14.16 Example of Inter-Processor Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A) .......................................... 216
Figure 14.17 Sample Multiprocessor Serial Transmission Flowchart ........................................ 217
Figure 14.18 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 219
Figure 14.18 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 220
Figure 14.19 Example of SCI3 Reception Using Multiprocessor Format
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).............................. 221
Figure 14.20 Receive Data Sampling Timing in Asynchronous Mode ...................................... 224
Section 15 I²C Bus Interface 2 (IIC2)
Figure 15.1 Block Diagram of I²C Bus Interface 2..................................................................... 226
Figure 15.2 External Circuit Connections of I/O Pins ................................................................ 227
Figure 15.3 I²C Bus Formats ...................................................................................................... 238
Figure 15.4 I²C Bus Timing........................................................................................................ 238
Figure 15.5 Master Transmit Mode Operation Timing (1) ......................................................... 240
Figure 15.6 Master Transmit Mode Operation Timing (2) ......................................................... 240
Figure 15.7 Master Receive Mode Operation Timing (1)........................................................... 242
Figure 15.8 Master Receive Mode Operation Timing (2)........................................................... 242
Figure 15.9 Slave Transmit Mode Operation Timing (1) ........................................................... 243
Figure 15.10 Slave Transmit Mode Operation Timing (2) ......................................................... 244
Figure 15.11 Slave Receive Mode Operation Timing (1)........................................................... 245
Figure 15.12 Slave Receive Mode Operation Timing (2)........................................................... 245
Figure 15.13 Clocked Synchronous Serial Transfer Format....................................................... 246
Figure 15.14 Transmit Mode Operation Timing......................................................................... 247
Figure 15.15 Receive Mode Operation Timing .......................................................................... 248
Figure 15.16 Block Diagram of Noise Canceler......................................................................... 248
Figure 15.17 Sample Flowchart for Master Transmit Mode....................................................... 249
Rev. 1.00, 11/03, page xxii of xxviii