 English |
|
|
|
|
|
|
|
| HD64336900G Datasheet, PDF (135/408 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series | |||
| |||
| ◁ |
Increment address
Erase start
Disable WDT
*2
SWE bit â 1
Wait 1 µs
nâ1
Set EBR1
Enable WDT
ESU bit â 1
Wait 100 µs
E bit â 1
Wait 10 µs
E bit â 0
Wait 10 µs
ESU bit â 10
Wait 10 µs
Disable WDT
EV bit â 1
Wait 20 µs
Set block start address as verify address
H'FF dummy write to verify address
Wait 2 µs
*1
Read verify data
No
Verify data + all 1s ?
Yes
No
Last address of block ?
Yes
EV bit â 0
Wait 4 µs
EV bit â 0
Wait 4µs
nân+1
No
All erase block erased ?
Yes
Yes
SWE bit â 0
Wait 100 µs
Yes
n â¤100 ?
No
SWE bit â 0
Wait 100 µs
End of erasing
Erase failure
Notes: 1. The RTS instruction must not be used during a period between dummy writing of H'FF to a verify address and verify data reading.
2. When WDT is in use, disable it once.
Figure 7.4 Erase/Erase-Verify Flowchart
Rev. 1.00, 11/03, page 107 of 376
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese