HD64336900G Datasheet, PDF (286/408 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Table 16.2 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel
AN0
AN1
AN2
AN3
A/D Data Register to Be Stored Results of A/D Conversion
ADDRA
ADDRB
ADDRC
ADDRD
16.3.2 A/D Control/Status Register (ADCSR)
ADCSR consists of the control bits and conversion end status bits of the A/D converter.
Initial
Bit
Bit Name Value R/W Description
7
ADF
0
R/W A/D End Flag
[Setting conditions]
• When A/D conversion ends in single mode
• When A/D conversion ends on all the channels
selected in scan mode
[Clearing conditions]
6
ADIE
0
• When 0 is written after reading ADF = 1
R/W A/D Interrupt Enable
A/D conversion end interrupt (ADI) request enabled by
ADF when 1 is set
5
ADST
0
R/W A/D Start
Setting this bit to 1 starts A/D conversion. In single mode,
this bit is cleared to 0 automatically when conversion on
the specified channel is complete. In scan mode,
conversion continues sequentially on the specified
channels until this bit is cleared to 0 by software, a reset,
or a transition to standby mode.
4
SCAN
0
R/W Scan Mode
Selects single mode or scan mode as the A/D conversion
operating mode.
0: Single mode
1: Scan mode
Rev. 1.00, 11/03, page 258 of 376