HD64336900G Datasheet, PDF (278/408 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Mater receive mode
Clear TEND in ICSR
Clear TRS in ICCR1 to 0
Clear TDRE in ICSR
Clear ACKBT in ICIER to 0
Dummy-read ICDRR
Read RDRF in ICSR
No
RDRF=1 ?
Yes
Last receive ^Yes
- 1?
No
Read ICDRR
Set ACKBT in ICIER to 1
Set RCVD in ICCR1 to 1
Read ICDRR
Read RDRF in ICSR
No _{RDRF=1 ?}
Yes
Clear STOP in ICSR.
Write 0 to BBSY
and SCP
Read STOP in ICSR
No _{STOP=1 ?}
Yes
Read ICDRR
Clear RCVD in ICCR1 to 0
[1] Clear TEND, select master receive mode, and then clear TDRE.*
[1] ^{[2] Set acknowledge to the transmit device.*}
[3] Dummy-read ICDDR.*
[2] [4] Wait for 1 byte to be received
[3] ^{[5] Check whether it is the (last receive - 1).}
[6] Read the receive data last.
[4] ^{[7] Set acknowledge of the final byte. Disable continuous reception (RCVD = 1).}
[8] Read the (final byte - 1) of receive data.
[5] [9] Wait for the last byte to be receive.
[10] Clear the STOP flag.
[6]
[11] Issue the stop condition.
[12] Wait for the creation of stop condition.
[7] [13] Read the last byte of receive data.
[14] Clear RCVD.
[8] _{[15] Set slave receive mode.}
[9]
[10]
[11]
[12]
[13]
[14]
Clear MST in ICCR1 to 0
[15]
End
Note: Do not activate an interrupt during the execution of steps [1] to [3].
When one byte is received, steps [2] to [6] are skipped after step [1],
before jumping to step [7]. The step [8] is dammy-read in ICDRR.
Figure 15.18 Sample Flowchart for Master Receive Mode
Rev. 1.00, 11/03, page 250 of 376