HD64336900G Datasheet, PDF (262/408 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

Bit Bit Name Initial Value R/W Description
0 ACKBT 0
R/W Transmit Acknowledge
In receive mode, this bit specifies the bit to be sent at the
acknowledge timing.
0: 0 is sent at the acknowledge timing.
1: 1 is sent at the acknowledge timing.
15.3.5 I²C Bus Status Register (ICSR)
ICSR performs confirmation of interrupt request flags and status.
Bit Bit Name Initial Value R/W Description
7 TDRE
0
R/W Transmit Data Register Empty
[Setting conditions]
• When data is transferred from ICDRT to ICDRS and
ICDRT becomes empty
• When TRS is set
• When a start condition (including re-transfer) has been
issued
• When transmit mode is entered from receive mode in
slave mode
[Clearing conditions]
• When 0 is written in TDRE after reading TDRE = 1
• When data is written to ICDRT with an instruction
6 TEND
0
R/W Transmit End
[Setting conditions]
• When the ninth clock of SCL rises with the I²C bus format
while the TDRE flag is 1
• When the final bit of transmit frame is sent with the clock
synchronous serial format
[Clearing conditions]
• When 0 is written in TEND after reading TEND = 1
• When data is written to ICDRT with an instruction
Rev. 1.00, 11/03, page 234 of 376