HD64336900G Datasheet, PDF(303/408 Page) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

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HD64336900G Datasheet, PDF (303/408 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

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Vint (U)

Vcc

Vint (D)

Vreset1

VSS

LVDDE

LVDDF

LVDUE

LVDUF

IRQ0 interrupt generated IRQ0 interrupt generated

Figure 17.5 Operational Timing of LVDI Circuit

Low Voltage Detection Interrupt (LVDI) Circuit

(When Voltages Input via ExtU and ExtD Pins are used for Detection):

Figure 17.6 shows the timing of the LVDI circuit. The LVDI circuit is enabled after a power-on

reset, however, the interrupt request is disabled. To enable the LVDI, the LVDDF and LVDUF

bits in LVDSR must be cleared to 0 and the LVDDE or LVDUE bit in LVDCR must be set to 1.

When using external compared voltage, write 0 to the VDDII bit in LVDCR, and wait for 50 Âµs

(tLVDON) given by a software timer until the detection circuit has settled. Then clear the LVDDF

and LVDUF bits to 0 and set the LVDDE or LVDUE bit to 1. After that, the output settings of

ports must be made. The initial value of the external compared voltages input on the ExtU and

ExtD pins must be higher than the Vexd voltage.

To cancel the LVDI, follow the procedures written in section 17.3.2 (4), Operating Procedures for

Enabling/Disabling LVDR and LVDI Circuits.

When the external comparison voltage of ExtD pin falls below the Vexd (D) (Typ. = 1.15 V)

voltage, the LVDI clears the LVDINT signal to 0 and sets the LVDDF bit in LVDSR to 1. If the

LVDDE bit is 1 at this time, an IRQ0 interrupt request is generated. In this case, the necessary

data must be saved in the external EEPROM, and a transition to standby mode or subsleep mode

must be made. Until this processing is completed, the power supply voltage must be higher than

the lower limit of the guaranteed operating voltage.

When the power-supply voltage does not fall below the Vreset1 (Typ. = 2.3 V) voltage and the

input voltage of the ExtU pin rises above Vexd (Typ. = 1.15 V) voltage, the LVDI circuit sets the

LVDINT signal to 1. If the LVDUE bit is 1 at this time, the LVDUF bit in LVDSR is set to 1 and

an IRQ0 interrupt request is generated.

Rev. 1.00, 11/03, page 275 of 376

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