HD64336900G Datasheet, PDF (119/408 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series

6.2.2 Standby Mode
In standby mode, the system clock oscillator is halted, and operation of the CPU and on-chip
peripheral modules is halted. However, as long as the rated voltage is supplied, the contents of
CPU registers, on-chip RAM, and some on-chip peripheral module registers are retained. On-chip
RAM contents will be retained as long as the voltage set by the RAM data retention voltage is
provided. The I/O ports go to the high-impedance state.
Standby mode is cleared by an interrupt. When an interrupt is requested, the internal RC oscillator
starts functioning. The external oscillator also starts functioning when used. After the time set by
the STS2 to STS0 bits in SYSCR1 has elapsed, standby mode is cleared and the CPU starts
interrupt exception handling. Standby mode is not cleared if the I bit in the condition code register
(CCR) is set to 1 or the requested interrupt is disabled by the interrupt enable bit.
When the RES pin is driven low in standby mode, the internal RC oscillator starts functioning.
The RC clock is supplied to the entire chip as soon as the internal RC oscillator starts functioning.
The RES pin must be kept low for the rated period. On driving the RES pin high, after the
oscillation stabilization time set by the power-on reset circuit has elapsed, the internal reset signal
is cleared and the CPU starts reset exception handling.
6.2.3 Subsleep Mode
In subsleep mode, the system clock oscillator is halted, and operation of the CPU and on-chip
peripheral modules is halted. However, as long as the rated voltage is supplied, the contents of
CPU registers, the on-chip RAM, and some on-chip peripheral module registers are retained. The
I/O ports keep the same states as before the transition.
Subsleep mode is cleared by an interrupt. When an interrupt is requested, the internal RC
oscillator starts functioning. The external oscillator also starts functioning when used. After the
time set by the STS2 to STS0 bits in SYSCR1 has elapsed, subsleep mode is cleared and the CPU
starts interrupt exception handling. Subsleep mode is not cleared if the I bit in the condition code
register (CCR) is set to 1 or the requested interrupt is disabled by the interrupt enable bit.
When the RES pin is driven low in subsleep mode, the internal RC oscillator starts functioning.
The RC clock is supplied to the entire chip as soon as the internal RC oscillator starts functioning.
The RES pin must be kept low for the rated period. On driving the RES pin high, after the
oscillation stabilization time set by the power-on reset circuit has elapsed, the internal reset signal
is cleared and the CPU starts reset exception handling.
Rev. 1.00, 11/03, page 91 of 376