MC68HC08AB16A Datasheet, PDF (78/380 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Mask Options (MOR)
6.5 Mask Option Register B
Address: $003F
Bit 7
6
5
4
3
2
1
Bit 0
Read: R EEDIVCLK EESEC EEMONSEC R
R
R
R
Write:
Reset:
Unaffected by reset
R = Reserved
Figure 6-2. Mask Option Register B (MORB))
EEDIVCLK — EEPROM Timebase Divider Clock Select Bit
EEDIVCLK selects the reference clock source for the EEPROM
timebase divider. (See Section 5. EEPROM.)
1 = CPU bus clock drives the EEPROM timebase divider
0 = CGMXCLK drives the EEPROM timebase divider
EESEC — EEPROM Security Enable Bit
When EESEC is set, the EEPROM protection bit, EEPRTCT, in the
EEPROM non-volatile register ($FE1C) can be used for EEPROM
protection. (See 5.7 EEPROM Security Options.)
1 = EEPROM security depends on EEPRTCT bit
0 = EEPROM security disabled
EEMONSEC — EEPROM Security in Monitor Mode Bit
When EEMONSEC is set, the entire EEPROM array cannot be
accessed in monitor mode, unless a valid security code is entered.
1 = EEPROM security enabled in monitor mode
0 = EEPROM security disabled in monitor mode
Extra care should be exercised when selecting the mask options
for ROM code submission. Ensure that the selected mask options
match exactly the setting in the CONFIG register of the emulation
part. The enable/disable logic is not necessarily identical in all
parts of the AB, AS, and AZ families. If in doubt, check with your
local field applications representative.
Technical Data
78
MC68HC08AB16A — Rev. 2.0
Mask Options (MOR)
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