MC68HC08AB16A Datasheet, PDF (73/380 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
EEPROM
EEPROM Registers
These two read/write registers are respectively loaded with the contents
of the EEPROM timebase divider mask option registers (EEDIVHMOR
and EEDIVLMOR) after a reset.
Address: $FE1A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
EEDIVSECD
R
R
R
R EEDIV10 EEDIV9 EEDIV8
Write:
Reset:
Contents of EEDIVHMOR ($FE10)
Figure 5-5. EEPROM Divider Register High (EEDIVH)
Address: $FE1B
Bit 7
6
5
4
3
2
1
Bit 0
Read:
EEDIV7 EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0
Write:
Reset:
Contents of EEDIVLMOR ($FE11)
Figure 5-6. EEPROM Divider Register Low (EEDIVL)
EEDIVSECD — EEPROM Divider Security Disable
This bit enables/disables the security feature of the EEDIV registers.
When EEDIV security feature is enabled, the state of the registers
EEDIVH and EEDIVL are locked (including this EEDIVSECD bit).
1 = EEDIV security feature disabled
0 = EEDIV security feature enabled
EEDIV[10:0] — EEPROM Timebase Prescaler
These prescaler bits store the value of EEDIV which is used as the
divisor to derive a timebase of 35µs from the selected reference clock
source (CGMXCLK or bus clock, see 6.5 Mask Option Register B)
for the EEPROM related internal timer and circuits. EEDIV[10:0] bits
are readable at any time. They are writable when EELAT=0 and
EEDIVSECD = 1.
The EEDIV value is calculated by the following formula:
EEDIV = INT [Reference frequency (Hz) × 35 × 10^–6 + 0.5]
MC68HC08AB16A — Rev. 2.0
MOTOROLA
EEPROM
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Technical Data
73