MC68HC08AB16A Datasheet, PDF (76/380 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Mask Options (MOR)
6.3 Functional Description
The two mask option registers (MORA and MORB) and two EEPROM
timebase divider mask option registers (EEDIVHMOR and
EEDIVLMOR) are read-only registers, and are used in the initialization
of various options. These registers are hard-wired connections specified
at the same time as the ROM code. The MORA and MORB registers are
located at $001F and $003F respectively. The EEDIVHMOR and
EEDIVLMOR are located at $FE10 and $FE11 respectively.
6.4 Mask Option Register A
Address: $001F
Bit 7
6
5
4
3
2
1
Read: LVISTOP SEC LVIRSTD LVIPWRD SSREC COPRS STOP
Write:
Reset:
Unaffected by reset
Figure 6-1. Mask Option Register A (MORA)
Bit 0
COPD
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the
LVI to operate in stop mode. Reset clears LVISTOP.
(See Section 21. Low-Voltage Inhibit (LVI).)
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
SEC — ROM Security Bit
When the SEC bit is set, ROM security is enabled, ROM content
cannot be dumped if security bypass fails on entering monitor mode.
(See 10.5 Security.)
1 = ROM security enabled
0 = ROM security disabled
LVIRSTD — LVI Reset Disable Bit
LVIRSTD disables the reset signal from the LVI module.
(See Section 21. Low-Voltage Inhibit (LVI).)
1 = LVI module resets disabled
0 = LVI module resets enabled
Technical Data
76
MC68HC08AB16A — Rev. 2.0
Mask Options (MOR)
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