MC68HC08AB16A Datasheet, PDF (346/380 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Computer Operating Properly (COP)
20.3 Functional Description
Figure 20-1 shows the structure of the COP module.
CGMXCLK
12-BIT COP PRESCALER
RESET CIRCUIT
RESET STATUS REGISTER
STOP INSTRUCTION
INTERNAL RESET SOURCES
RESET VECTOR FETCH
COPCTL WRITE
COPEN (FROM SIM)
COP DISABLE
(COPD FROM MORA)
RESET
COPCTL WRITE
COP RATE SEL
(COPRS FROM MORA)
COP CLOCK
COP MODULE
6-BIT COP COUNTER
CLEAR
COP COUNTER
Figure 20-1. COP Block Diagram
The COP counter is a free-running 6-bit counter preceded by a 12-bit
prescaler counter. If not cleared by software, the COP counter overflows
and generates an asynchronous reset after 2¹⁸ – 2⁴ or 2¹³ – 2⁴
CGMXCLK cycles, depending on the state of the COP rate select bit,
COPRS, in mask option register A (MORA). With a 2¹⁸ – 2⁴ CGMXCLK
cycle overflow option, a 4.9152MHz crystal gives a COP timeout period
of 53.3ms. Writing any value to location $FFFF before an overflow
occurs prevents a COP reset by clearing the COP counter and stages
12 through 5 of the prescaler.
NOTE:
Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
Technical Data
346
MC68HC08AB16A — Rev. 2.0
Computer Operating Properly (COP)
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