MC68HC08AB16A Datasheet, PDF (143/380 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
CGM During Break Interrupts
9.8.2 Stop Mode
When the STOP instruction executes, the SIM drives the SIMOSCEN
signal low, disabling the CGM and holding low all CGM outputs
(CGMXCLK, CGMOUT, and CGMINT).
If the STOP instruction is executed with the VCO clock, CGMVCLK,
divided by two driving CGMOUT, the PLL automatically clears the BCS
bit in the PLL control register (PCTL), thereby selecting the crystal
clock, CGMXCLK, divided by two as the source of CGMOUT. When the
MCU recovers from STOP, the crystal clock divided by two drives
CGMOUT and BCS remains clear.
9.9 CGM During Break Interrupts
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. See Section 8. System Integration
Module (SIM).
To allow software to clear status bits during a break interrupt, a 1
should be written to the BCFE bit. If a status bit is cleared during the
break state, it remains cleared when the MCU exits the break state.
To protect the PLLF bit during the break state, write a 0 to the BCFE bit.
With BCFE at 0 (its default state), software can read and write the PLL
control register during the break state without affecting the PLLF bit.
9.10 Acquisition/Lock Time Specifications
The acquisition and lock times of the PLL are, in many applications, the
most critical PLL design parameters. Proper design and use of the PLL
ensures the highest stability and lowest acquisition/lock times.
MC68HC08AB16A — Rev. 2.0
MOTOROLA
Clock Generator Module (CGM)
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Technical Data
143