MC68HC08AB16A Datasheet, PDF (363/380 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Break Module (BRK)
Break Module Registers
Address: $FE00
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SBSW
R
R
R
R
R
R
R
Write:
Note
Reset: 0
0
0
0
0
0
0
0
Note: Writing a logic 0 clears SBSW.
R = Reserved
Figure 22-6. SIM Break Status Register (SBSR)
SBSW — SIM Break Stop/Wait Bit
This status bit is useful in applications requiring a return to wait or stop
mode after exiting from a break interrupt. Clear SBSW by writing a
logic 0 to it. Reset clears SBSW.
1 = Stop mode or wait mode was exited by break interrupt
0 = Stop mode or wait mode was not exited by break interrupt
SBSW can be read within the break interrupt routine. The user can
modify the return address on the stack by subtracting one from it. The
following code is an example.
;This code works if the H register has been pushed onto the stack in the break
;service routine software. This code should be executed at the end of the break
;service routine software.
HIBYTE EQU
5
LOBYTE EQU
6
;
If not SBSW, do RTI
BRCLR SBSW,SBSR, RETURN
;See if wait mode or stop mode was exited by
;break.
TST
LOBYTE,SP
;If RETURNLO is not zero,
BNE
DOLO
;then just decrement low byte.
DEC
HIBYTE,SP
;Else deal with high byte, too.
DOLO
DEC
LOBYTE,SP
;Point to WAIT/STOP opcode.
RETURN PULH
RTI
;Restore H register.
MC68HC08AB16A — Rev. 2.0
MOTOROLA
Break Module (BRK)
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Technical Data
363