MC68HC08AB16A Datasheet, PDF (230/380 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Analog-to-Digital Converter (ADC)
Table 14-2. ADC Clock Divide Ratio
ADIV2 ADIV1
0
0
0
0
0
1
0
1
1
X
X = don’t care
ADIV0
0
1
0
1
X
ADC Clock Rate
ADC input clock ÷ 1
ADC input clock ÷ 2
ADC input clock ÷ 4
ADC input clock ÷ 8
ADC input clock ÷ 16
ADICLK — ADC Input Clock Select Bit
ADICLK selects either the bus clock or CGMXCLK as the input clock
source to generate the internal ADC clock. Reset selects CGMXCLK
as the ADC clock source.
If the external clock (CGMXCLK) is equal to or greater than 1 MHz,
CGMXCLK can be used as the clock source for the ADC. If
CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as
the clock source. As long as the internal ADC clock is at
approximately 1 MHz, correct operation can be guaranteed.
1 = Internal bus clock
0 = External clock (CGMXCLK)
-A----D-----C------i-n----p--A-u---Dt----c-I--lV-o---c[--2-k--:--0-f--r]--e---q---u----e---n----c---y- = 1MHz
Technical Data
230
MC68HC08AB16A — Rev. 2.0
Analog-to-Digital Converter (ADC)
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