MC68HC08AB16A Datasheet, PDF (316/380 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Input/Output (I/O) Ports
17.6.2 Data Direction Register D (DDRD)
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic 1 to a DDRD bit enables the output buffer
for the corresponding port D pin; a logic 0 disables the output buffer.
Address: $0007
Bit 7
6
5
4
3
2
1
Read:
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1
Write:
Reset: 0
0
0
0
0
0
0
Figure 17-12. Data Direction Register D (DDRD)
Bit 0
DDRD0
0
DDRD[7:0] — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears
DDRD[7:0], configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE:
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1. Figure 17-13 shows
the port D I/O logic.
READ DDRD ($0007)
V_DD
WRITE DDRD ($0007)
RESET
WRITE PTD ($0003)
DDRDx
PTDx
PTDPUEx
PTDx
READ PTD ($0003)
Technical Data
316
PTD6 to TACLK of TIMA
PTD4 to TBCLK of TIMB
Figure 17-13. Port D I/O Circuit
MC68HC08AB16A — Rev. 2.0
Input/Output (I/O) Ports
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA