MC68HC08AB16A Datasheet, PDF (54/380 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Memory Map
Freescale Semiconductor, Inc.
Addr.
Register Name
Bit 7
6
5
4
3
2
1
$FE0A
Read:
R
R
R
R
R
R
R
Reserved Write:
Reset:
$FE0B
Read:
R
R
R
R
R
R
R
Reserved Write:
Reset:
Break Address Register ^Read: _{Bit 15}
14
13
12
11
10
9
$FE0C
High Write:
(BRKH) _{Reset: 0}
0
0
0
0
0
0
Break Address Register ^Read: _{Bit 7}
6
5
4
3
2
1
$FE0D
Low Write:
(BRKL) _{Reset: 0}
0
0
0
0
0
0
Break Status and Control ^Read: _{BRKE BRKA}
0
0
0
0
0
$FE0E
Register Write:
(BRKSCR) _{Reset: 0}
0
0
0
0
0
0
Low-Voltage Inhibit Status ^{Read: LVIOUT}
0
0
0
0
0
0
$FE0F
Register Write:
(LVISR) _{Reset: 0}
0
0
0
0
0
0
$FE10
EEDIV Mask Option ^{Read: EEDIVSECD R}
Register High Write:
(EEDIVHMOR)^† _Reset:
R
R
R EEDIV10 EEDIV9
Unaffected by reset; mask option
$FE11
EEDIV Mask Option ^Read:
Register Low Write:
(EEDIVLMOR)^† _Reset:
EEDIV7
EEDIV6
EEDIV5 EEDIV4 EEDIV3 EEDIV2
Unaffected by reset; mask option
EEDIV1
† Hard-wired register, specified during ROM code submission.
Read:
$FE1A
EE Divider Register High
(EEDIVH)
EEDIVSECD
Write:
R
Reset:
R
R
R EEDIV10 EEDIV9
Contents of EEDIVHMOR ($FE10)
$FE1B
Read:
EE Divider Register Low
(EEDIVL)
Write:
Reset:
EEDIV7
EEDIV6
EEDIV5 EEDIV4 EEDIV3 EEDIV2
Contents of EEDIVLMOR ($FE11)
EEDIV1
= Unimplemented
R = Reserved
Bit 0
R
R
Bit 8
0
Bit 0
0
0
0
0
0
EEDIV8
EEDIV0
EEDIV8
EEDIV0
Figure 2-2. Control, Status, and Data Registers (Sheet 10 of 11)
Technical Data
54
MC68HC08AB16A — Rev. 2.0
Memory Map
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