MC68HC08AB16A Datasheet, PDF (217/380 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Programmable Interrupt Timer (PIT)
I/O Registers
bits. Some status bits have a two-step read/write clearing procedure. If
software does the first step on such a bit before the break, the bit cannot
change during the break state as long as BCFE is at logic zero. After the
break, doing the second step clears the status bit.
13.7 I/O Registers
The following I/O registers control and monitor operation of the PIT:
• PIT status and control register (PSC)
• PIT counter registers (PCNTH:PCNTL)
• PIT counter modulo registers (PMODH:PMODL)
13.7.1 PIT Status and Control Register
The PIT status and control register does the following:
• Enables PIT interrupt
• Flags PIT overflows
• Stops the PIT counter
• Resets the PIT counter
• Prescales the PIT counter clock
Address: $004B
Bit 7
6
5
4
3
2
1
Read: POF
0
0
POIE PSTOP
PPS2 PPS1
Write: 0
PRST
Reset: 0
0
1
0
0
0
0
= Unimplemented
Figure 13-3. PIT Status and Control Register (PSC)
Bit 0
PPS0
0
MC68HC08AB16A — Rev. 2.0
MOTOROLA
Programmable Interrupt Timer (PIT)
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Technical Data
217