MC68HC08AB16A Datasheet, PDF (140/380 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
The crystal loss detect function works only when the BCS bit is set,
selecting CGMVCLK to drive CGMOUT. When BCS is clear, XLD
always reads as 0.
Bits [3:0] — Reserved for test
These bits enable test functions not available in user mode. To ensure
software portability from development systems to user applications,
software should write zeros to Bits [3:0] whenever writing to PBWC.
9.6.3 PLL Programming Register (PPG)
The PLL programming register contains the programming information
for the modulo feedback divider and the programming information for
the hardware configuration of the VCO.
Address: $001E
Bit 7
6
5
4
3
2
1
Read:
MUL7
Write:
MUL6
MUL5
MUL4
VRS7
VRS6
VRS5
Reset: 0
1
1
0
0
1
1
Figure 9-8. PLL Programming Register (PPG)
Bit 0
VRS4
0
MUL[7:4] — Multiplier Select Bits
These read/write bits control the modulo feedback divider that
selects the VCO frequency multiplier, N. (See 9.4.2.1 PLL Circuits
and 9.4.2.4 Programming the PLL). A value of $0 in the multiplier
select bits configures the modulo feedback divider the same as a
value of $1. Reset initializes these bits to $6 to give a default multiply
value of 6.
Technical Data
140
MC68HC08AB16A — Rev. 2.0
Clock Generator Module (CGM)
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