MC68HC08AB16A Datasheet, PDF (106/380 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
System Integration Module (SIM)
All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in
monitor mode) and assert the internal reset signal (IRST). IRST causes
all registers to be returned to their default values and all modules to be
returned to their reset states.
An internal reset clears the SIM counter (see 8.5 SIM Counter), but an
external reset does not. Each of the resets sets a corresponding bit in
the SIM reset status register (SRSR). (See 8.8 SIM Registers.)
8.4.1 External Pin Reset
Pulling the asynchronous RST pin low halts all processing. The PIN bit
of the SIM reset status register (SRSR) is set as long as RST is held low
for a minimum of 67 CGMXCLK cycles, assuming that neither the POR
nor the LVI was the source of the reset. See Table 8-2 for details.
Figure 8-4 shows the relative timing.
Table 8-2. PIN Bit Set Timing
Reset Type
POR/LVI
All others
Number of Cycles Required to Set PIN
4163 (4096 + 64 + 3)
67 (64 + 3)
CGMOUT
RST
IAB PC
VECT H VECT L
Figure 8-4. External Reset Timing
8.4.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK
cycles to allow for resetting of external peripherals. The internal reset
signal IRST continues to be asserted for an additional 32 cycles. See
Figure 8-5. An internal reset can be caused by an illegal address, illegal
opcode, COP timeout, LVI, or POR. See Figure 8-6. Note that for LVI or
POR resets, the SIM cycles through 4096 CGMXCLK cycles, during
which the SIM forces the RST pin low. The internal reset signal then
follows the sequence from the falling edge of RST as shown in
Figure 8-5.
Technical Data
106
MC68HC08AB16A — Rev. 2.0
System Integration Module (SIM)
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