MC68HC08AB16A Datasheet, PDF (136/380 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
Addr. Register Name
Bit 7
6
5
4
3
Read:
PLLF
1
$001C
PLL Control Register
(PCTL)
Write:
PLLIE
PLLON BCS
Reset: 0
0
1
0
1
Read:
LOCK
0
PLL Bandwidth Control
AUTO
ACQ
XLD
$001D
Register Write:
(PBWC)
Reset: 0
0
0
0
0
$001E
Read:
PLL Programming
Register Write:
(PPG)
Reset:
MUL7
0
MUL6
1
MUL5
1
MUL4
0
VRS7
0
= Unimplemented
NOTES:
1. When AUTO = 0, PLLIE is forced to logic zero and is read-only.
2. When AUTO = 0, PLLF and LOCK read as logic zero.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS[7:4] = $0, BCS is forced to logic zero and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
Figure 9-4. CGM I/O Register Summary
2
1
1
0
0
VRS6
1
1
1
1
0
0
VRS5
1
Bit 0
1
1
0
0
VRS4
0
9.6.1 PLL Control Register (PCTL)
The PLL control register contains the interrupt enable and flag bits, the
on/off switch, and the base clock selector bit.
Address: $001C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PLLF
1
1
1
1
PLLIE
PLLON BCS
Write:
Reset: 0
0
1
0
1
1
1
1
= Unimplemented
Figure 9-5. PLL Control Register (PCTL)
Technical Data
136
MC68HC08AB16A — Rev. 2.0
Clock Generator Module (CGM)
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