MC68HC08AB16A Datasheet, PDF (127/380 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
Functional Description
9.4.2 Phase-Locked Loop (PLL) Circuit
The PLL is a frequency generator that can operate in either acquisition
mode or tracking mode, depending on the accuracy of the output
frequency. The PLL can change between acquisition and tracking
modes either automatically or manually.
9.4.2.1 PLL Circuits
The PLL consists of the following circuits:
• Voltage-controlled oscillator (VCO)
• Modulo VCO frequency divider
• Phase detector
• Loop filter
• Lock detector
The operating range of the VCO is programmable for a wide range of
frequencies and for maximum immunity to external noise, including
supply and CGMXFC noise. The VCO frequency is bound to a range
from roughly one-half to twice the center-of-range frequency, f_VRS.
Modulating the voltage on the CGMXFC pin changes the frequency
within this range. By design, f_VRS is equal to the nominal center-of-range
frequency, f_NOM, (4.9152MHz) times a linear factor L, or (L)f_NOM.
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.
CGMRCLK runs at a frequency f_RCLK, and is fed to the PLL through a
buffer. The buffer output is the final reference clock, CGMRDV, running
at a frequency f_RDV = f_RCLK.
The VCO’s output clock, CGMVCLK, running at a frequency f_VCLK, is fed
back through a programmable modulo divider. The modulo divider
reduces the VCO clock by a factor N. The divider’s output is the VCO
feedback clock, CGMVDV, running at a frequency f_VDV = f_VCLK/N. (See
9.4.2.4 Programming the PLL for more information).
The phase detector then compares the VCO feedback clock, CGMVDV,
with the final reference clock, CGMRDV. A correction pulse is generated
based on the phase difference between the two signals. The loop filter
MC68HC08AB16A — Rev. 2.0
MOTOROLA
Clock Generator Module (CGM)
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Technical Data
127