MC68HC08AB16A Datasheet, PDF (77/380 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Mask Options (MOR)
Mask Option Register A
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module.
(See Section 21. Low-Voltage Inhibit (LVI).)
1 = LVI module power disabled
0 = LVI module power enabled
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32
CGMXCLK cycles instead of a 4096 CGMXCLK cycle delay.
1 = STOP mode recovery after 32 CGMXCLK cycles
0 = STOP mode recovery after 4096 CGMXCLK cycles
NOTE: If using an external crystal oscillator, do not set the SSREC bit.
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS.
(See Section 20. Computer Operating Properly (COP).)
1 = COP timeout period is 2¹⁸ – 2⁴ CGMXCLK cycles
0 = COP timeout period is 2¹³ – 2⁴ CGMXCLK cycles
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module.
(See Section 20. Computer Operating Properly (COP).)
1 = COP module disabled
0 = COP module enabled
Extra care should be exercised when selecting the mask options
for ROM code submission. Ensure that the selected mask options
match exactly the setting in the CONFIG register of the emulation
part. The enable/disable logic is not necessarily identical in all
parts of the AB, AS, and AZ families. If in doubt, check with your
local field applications representative.
MC68HC08AB16A — Rev. 2.0
MOTOROLA
Mask Options (MOR)
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Technical Data
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