MC68HC08AB16A Datasheet, PDF (111/380 Pages) Motorola, Inc – HCMOS Microcontroller Unit

8.6.1 Interrupts
Freescale Semiconductor, Inc.
System Integration Module (SIM)
Exception Control
At the beginning of an interrupt, the CPU saves the CPU register
contents onto the stack and sets the interrupt mask (I-bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume. Figure 8-8 shows interrupt entry timing, and
Figure 8-9 shows interrupt recovery timing.
MODULE
INTERRUPT
I-BIT
IAB
IDB
R/W
MODULE
INTERRUPT
I-BIT
IAB
IDB
R/W
DUMMY
SP
SP – 1 SP – 2 SP – 3 SP – 4 VECT H VECT L START ADDR
DUMMY PC – 1[7:0] PC – 1[15:8] X
A
CCR V DATA H V DATA L OPCODE
Figure 8-8. Interrupt Entry Timing
SP – 4 SP – 3 SP – 2 SP – 1
SP
PC
PC + 1
CCR
A
X
PC – 1[7:0] PC – 1[15:8] OPCODE OPERAND
Figure 8-9. Interrupt Recovery Timing
Interrupts are latched, and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt may take precedence, regardless of priority,
until the latched interrupt is serviced (or the I-bit is cleared).
(See Figure 8-10.)
MC68HC08AB16A — Rev. 2.0
MOTOROLA
System Integration Module (SIM)
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Technical Data
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