MC68HC08AB16A Datasheet, PDF (147/380 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
Acquisition/Lock Time Specifications
but the PLL may become unstable. Also, always choose a capacitor
with a tight tolerance (±20% or better) and low dissipation.
9.10.4 Reaction Time Calculation
The actual acquisition and lock times can be calculated using the
equations below. These equations yield nominal values under the
following conditions:
• Correct selection of filter capacitor, C_F,
(see 9.10.3 Choosing a Filter Capacitor)
• Room temperature operation
• Negligible external leakage on CGMXFC
• Negligible noise
The K factor in the equations is derived from internal PLL parameters.
K_ACQ is the K factor when the PLL is configured in acquisition mode, and
K_TRK is the K factor when the PLL is configured in tracking mode. See
9.4.2.2 Acquisition and Tracking Modes.
t_ACQ
=


V--f--_{R-D--D-D--V-A-}


-K----_A-8--_C---_Q- _
t_AL
=


V--f--_{R-D--D-D--V-A-}


K-----_T^4---_R^---_K^{-}
t_LOCK = t_ACQ + t_AL
Note the inverse proportionality between the lock time and the
reference frequency.
In automatic bandwidth control mode the acquisition and lock times are
quantized into units based on the reference frequency. See 9.4.2.3
MC68HC08AB16A — Rev. 2.0
MOTOROLA
Clock Generator Module (CGM)
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Technical Data
147