English
Language : 

MC68HC08AB16A Datasheet, PDF (129/380 Pages) Motorola, Inc – HCMOS Microcontroller Unit
Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
Functional Description
In automatic bandwidth control mode (AUTO = 1), the lock detector
automatically switches between acquisition and tracking modes.
Automatic bandwidth control mode is used also to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock,
CGMOUT. See 9.6.2 PLL Bandwidth Control Register (PBWC). If PLL
interrupts are enabled, the software can wait for a PLL interrupt request
and then check the LOCK bit. If interrupts are disabled, software can
poll the LOCK bit continuously (during PLL start-up, usually) or at
periodic intervals. In either case, when the LOCK bit is set, the VCO
clock is safe to use as the source for the base clock. See 9.4.3 Base
Clock Selector Circuit. If the VCO is selected as the source for the
base clock and the LOCK bit is clear, the PLL has suffered a severe
noise hit and the software must take appropriate action, depending on
the application. (See 9.7 Interrupts for information and precautions on
using interrupts). The following conditions apply when the PLL is in
automatic bandwidth control mode:
• The ACQ bit (see 9.6.2 PLL Bandwidth Control Register
(PBWC)) is a read-only indicator of the mode of the filter. (See
9.4.2.2 Acquisition and Tracking Modes)
• The ACQ bit is set when the VCO frequency is within a certain
tolerance ∆TRK and is cleared when the VCO frequency is out of a
certain tolerance ∆UNT. (See 9.10 Acquisition/Lock Time
Specifications)
• The LOCK bit is a read-only indicator of the locked state of the
PLL.
• The LOCK bit is set when the VCO frequency is within a certain
tolerance ∆LOCK and is cleared when the VCO frequency is out of
a certain tolerance ∆UNL. (See 9.10 Acquisition/Lock Time
Specifications)
• CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s
lock condition changes, toggling the LOCK bit. (See 9.6.1 PLL
Control Register (PCTL))
The PLL also may operate in manual mode (AUTO = 0). Manual mode
is used by systems that do not require an indicator of the lock condition
for proper operation. Such systems typically operate well below fBUSMAX
MC68HC08AB16A — Rev. 2.0
MOTOROLA
Clock Generator Module (CGM)
For More Information On This Product,
Go to: www.freescale.com
Technical Data
129