MC68HC08AB16A Datasheet, PDF (145/380 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
Acquisition/Lock Time Specifications
• Lock time, t_LOCK, is the time the PLL takes to reduce the error
between the actual output frequency and the desired output
frequency to less than the lock mode entry tolerance ∆_LOCK. Lock
time is based on an initial frequency error, (f_DES – f_ORIG)/f_DES, of
not more than ±100%. In automatic bandwidth control mode, lock
time expires when the LOCK bit becomes set in the PLL
bandwidth control register (PBWC). See 9.4.2.3 Manual and
Automatic PLL Bandwidth Modes.
Obviously, the acquisition and lock times can vary according to how
large the frequency error is and may be shorter or longer in many
cases.
9.10.2 Parametric Influences On Reaction Time
Acquisition and lock times are designed to be as short as possible
while still providing the highest possible stability. These reaction times
are not constant, however. Many factors directly and indirectly affect the
acquisition time.
The most critical parameter which affects the reaction times of the PLL
is the reference frequency, f_RDV. This frequency is the input to the
phase detector and controls how often the PLL makes corrections. For
stability, the corrections must be small compared to the desired
frequency, so several corrections are required to reduce the frequency
error. Therefore, the slower the reference the longer it takes to make
these corrections. This parameter is also under user control via the
choice of crystal frequency f_XCLK.
Another critical parameter is the external filter capacitor. The PLL
modifies the voltage on the VCO by adding or subtracting charge from
this capacitor. Therefore, the rate at which the voltage changes for a
given frequency error (thus change in charge) is proportional to the
capacitor size. The size of the capacitor also is related to the stability of
the PLL. If the capacitor is too small, the PLL cannot make small
enough adjustments to the voltage and the system cannot lock. If the
capacitor is too large, the PLL may not be able to adjust the voltage in
a reasonable time. See 9.10.3 Choosing a Filter Capacitor.
MC68HC08AB16A — Rev. 2.0
MOTOROLA
Clock Generator Module (CGM)
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Technical Data
145