MC68HC08AB16A Datasheet, PDF (178/380 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Timer Interface Module A (TIMA)
PS[2:0] — Prescaler Select Bits
These read/write bits select either the PTD6/TACLK pin or one of the
seven prescaler outputs as the input to the TIMA counter as
Table 11-2 shows. Reset clears the PS[2:0] bits.
Table 11-2. Prescaler Selection
PS2 PS1 PS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
TIM Clock Source
Internal Bus Clock ÷1
Internal Bus Clock ÷ 2
Internal Bus Clock ÷ 4
Internal Bus Clock ÷ 8
Internal Bus Clock ÷ 16
Internal Bus Clock ÷ 32
Internal Bus Clock ÷ 64
PTD6/TACLK
11.10.2 TIMA Counter Registers
The two read-only TIMA counter registers contain the high and low
bytes of the value in the TIMA counter. Reading the high byte
(TACNTH) latches the contents of the low byte (TACNTL) into a buffer.
Subsequent reads of TACNTH do not affect the latched TACNTL value
until TACNTL is read. Reset clears the TIMA counter registers. Setting
the TIMA reset bit (TRST) also clears the TIMA counter registers.
NOTE:
If you read TACNTH during a break interrupt, be sure to unlatch
TACNTL by reading TACNTL before exiting the break interrupt.
Otherwise, TACNTL retains the value latched during the break.
Address: $0022
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 11-5. TIMA Counter Register High (TACNTH)
Technical Data
178
MC68HC08AB16A — Rev. 2.0
Timer Interface Module A (TIMA)
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