MC68HC08AB16A Datasheet, PDF (352/380 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Low-Voltage Inhibit (LVI)
21.4 Functional Description
Figure 21-1 shows the structure of the LVI module. The LVI is enabled
out of reset. The LVI module contains a bandgap reference circuit and
comparator. The LVI power bit, LVIPWRD, enables the LVI to monitor
V_DD voltage. The LVI reset bit, LVIRSTD, enables the LVI module to
generate a reset when V_DD falls below a voltage, LVI_TRIPF, and remains
at or below that level for 9 or more consecutive CPU cycles. Setting the
LVI enable in stop mode bit, LVISTOP, enables the LVI to operate in stop
mode.
LVISTOP, LVIPWRD, and LVIRSTD are in the mask option register A
(MORA). See Section 6. Mask Options (MOR) for details of the LVI’s
configuration bits. Once an LVI reset occurs, the MCU remains in reset
until V_DD rises above a voltage, LVI_TRIPR, which causes the MCU to exit
reset. See 8.4.2.5 Low-Voltage Inhibit (LVI) Reset for details of the
interaction between the SIM and the LVI. The output of the comparator
controls the state of the LVIOUT flag in the LVI status register (LVISR).
An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices.
NOTE:
Where LVI trip falling voltage LVI_TRIPF = V_LVII
and LVI trip rising voltage LVI_TRIPR = V_LVII + H_LVI
(See Section 23. Electrical Specifications.)
V_DD
STOP INSTRUCTION
LVIPWRD
FROM MORA
FROM MORA
LVIRSTD
LVISTOP
FROM MORA
LOW V_DD
DETECTOR
V_DD > LVI_Trip = 0
V_DD ≤ LVI_Trip = 1
LVIOUT
TO LVISR
LVI RESET
Figure 21-1. LVI Module Block Diagram
Technical Data
352
MC68HC08AB16A — Rev. 2.0
Low-Voltage Inhibit (LVI)
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