MC68HC08AB16A Datasheet, PDF (118/380 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
System Integration Module (SIM)
A break interrupt during stop mode sets the SIM break STOP/WAIT bit
(SBSW) in the SIM break status register (SBSR).
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time the
recovery period. Figure 8-15 shows stop mode entry timing.
CPUSTOP
IAB STOP ADDR
STOP ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
instruction.
Figure 8-15. Stop Mode Entry Timing
CGMXCLK
INT/BREAK
IAB
STOP RECOVERY PERIOD
STOP +1
STOP + 2 STOP + 2
SP
SP – 1
SP – 2
SP – 3
Figure 8-16. Stop Mode Recovery from Interrupt or Break
Technical Data
118
MC68HC08AB16A — Rev. 2.0
System Integration Module (SIM)
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