MC68HC08AB16A Datasheet, PDF (219/380 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Programmable Interrupt Timer (PIT)
I/O Registers
PPS[2:0] — PIT Prescaler Select Bits
These read/write bits select one of the seven prescaler outputs as the
input to the PIT counter as Table 13-1 shows. Reset clears the
PPS[2:0] bits.
Table 13-1. PIT Prescaler Selection
PPS2
0
0
0
0
1
1
1
1
PPS1
0
0
1
1
0
0
1
1
PPS0
0
1
0
1
0
1
0
1
PIT Clock Source
Internal Bus Clock ÷1
Internal Bus Clock ÷ 2
Internal Bus Clock ÷ 4
Internal Bus Clock ÷ 8
Internal Bus Clock ÷ 16
Internal Bus Clock ÷ 32
Internal Bus Clock ÷ 64
Internal Bus Clock ÷ 64
13.7.2 PIT Counter Registers
The two read-only PIT counter registers contain the high and low bytes
of the value in the PIT counter. Reading the high byte (PCNTH) latches
the contents of the low byte (PCNTL) into a buffer. Subsequent reads of
PCNTH do not affect the latched PCNTL value until PCNTL is read.
Reset clears the PIT counter registers. Setting the PIT reset bit (PRST)
also clears the PIT counter registers.
NOTE:
If you read PCNTH during a break interrupt, be sure to unlatch PCNTL
by reading PCNTL before exiting the break interrupt. Otherwise, PCNTL
retains the value latched during the break.
Address: $004C
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 13-4. PIT Counter Register High (PCNTH)
MC68HC08AB16A — Rev. 2.0
MOTOROLA
Programmable Interrupt Timer (PIT)
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Technical Data
219