MC68HC08AB16A Datasheet, PDF (298/380 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Serial Peripheral Interface Module (SPI)
16.14.2 SPI Status and Control Register
The SPI status and control register contains flags to signal these
conditions:
• Receive data register full
• Failure to clear SPRF bit before next byte is received (overflow
error)
• Inconsistent logic level on SS pin (mode fault error)
• Transmit data register empty
The SPI status and control register also contains bits that perform these
functions:
• Enable error interrupts
• Enable mode fault error detection
• Select master SPI baud rate
Address: $0011
Bit 7
6
5
4
3
2
1
Bit 0
Read: SPRF
Write:
ERRIE
OVRF
MODF
SPTE
MODFEN SPR1
SPR0
Reset: 0
0
0
0
1
0
0
0
= Unimplemented
Figure 16-14. SPI Status and Control Register (SPSCR)
Technical Data
298
SPRF — SPI Receiver Full Bit
This clearable, read-only flag is set each time a byte transfers from
the shift register to the receive data register. SPRF generates a CPU
interrupt request if the SPRIE bit in the SPI control register is set also.
During an SPRF CPU interrupt, the CPU clears SPRF by reading the
SPI status and control register with SPRF set and then reading the
SPI data register. Reset clears the SPRF bit.
1 = Receive data register full
0 = Receive data register not full
MC68HC08AB16A — Rev. 2.0
Serial Peripheral Interface Module (SPI)
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