PIC18F87J10 Datasheet, PDF (89/394 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J10 FAMILY
7.2 Address and Data Width
The PIC18F87J10 family of devices can be indepen-
dently configured for different address and data widths
on the same memory bus. Both address and data width
are set by configuration bits in the CONFIG3L register.
As configuration bits, this means that these options can
only be configured by programming the device and are
not controllable in software.
The BW bit selects an 8-bit or 16-bit data bus width.
Setting this bit (default) selects a data width of 16 bits.
The EMB1:EMB0 bits determine both the program
memory operating mode and the address bus width.
The available options are 20-bit (default), 16-bit and
12-bit, as well as Microcontroller mode (external bus
disabled). Selecting a 16-bit or 12-bit width makes a
corresponding number of high-order lines available for
I/O functions; these pins are no longer affected by the
setting of the EBDIS bit. For example, selecting a 16-bit
Address mode (EMB1:EMB0 = 10) disables A19:A16
and allows PORTH<3:0> to function without interrup-
tions from the bus. Using the smaller address widths
allows users to tailor the memory bus to the size of the
external memory space for a particular design while
freeing up pins for dedicated I/O operation.
Because the EMB bits have the effect of disabling pins
for memory bus operations, it is important to always
select an address width at least equal to the data width.
If a 12-bit address width is used with a 16-bit data
width, the upper four bits of data will not be available on
the bus.
All combinations of address and data widths require
multiplexing of address and data information on the
same lines. The address and data multiplexing, as well
as I/O ports made available by the use of smaller
address widths, are summarized in Table 7-2.
7.2.1
ADDRESS SHIFTING ON THE
EXTERNAL BUS
By default, the address presented on the external bus
is the value of the PC. In practical terms, this means
that addresses in the external memory device below
the top of on-chip memory are unavailable to the micro-
controller. To access these physical locations, the glue
logic between the microcontroller and the external
memory must somehow translate addresses.
To simplify the interface, the external bus offers an
extension of Extended Microcontroller mode that
automatically performs address shifting. This feature is
controlled by the EASHFT configuration bit. Setting this
bit offsets addresses on the bus by the size of the
microcontroller’s on-chip program memory and sets
the bottom address at 0000h. This allows the device to
use the entire range of physical addresses of the
external memory.
7.2.2 21-BIT ADDRESSING
As an extension of 20-bit address width operation, the
external memory bus can also fully address a 2-Mbyte
memory space. This is done by using the Bus Address
Bit 0 (BA0) control line as the Least Significant bit of the
address. The UB and LB control signals may also be
used with certain memory devices to select the upper
and lower bytes within a 16-bit wide data word.
This addressing mode is available in both 8-bit and
certain 16-bit data width modes. Additional details are
provided in Section 7.6.3 “16-Bit Byte Select Mode”
and Section 7.7 “8-bit Mode”.
TABLE 7-2: ADDRESS AND DATA LINES FOR DIFFERENT ADDRESS AND DATA WIDTHS
Data Width
Address Width
Multiplexed Data and
Address-Only
Address Lines (and
Lines (and
Corresponding Ports) Corresponding Ports)
Ports Available
for I/O
8-bit
16-bit
12-bit
16-bit
20-bit
16-bit
20-bit
AD7:AD0
(PORTD<7:0>)
AD15:AD0
(PORTD<7:0>,
PORTE<7:0>)
AD11:AD8
(PORTE<3:0>)
AD15:AD8
(PORTE<7:0>)
A19:A16, AD15:AD8
(PORTH<3:0>,
PORTE<7:0>)
—
A19:A16
(PORTH<3:0>)
PORTE<7:4>,
All of PORTH
All of PORTH
—
All of PORTH
—
 2005 Microchip Technology Inc.
Advance Information
DS39663A-page 87