PIC18F87J10 Datasheet, PDF (111/394 Pages) Microchip Technology – 64/80-Pin High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology

PIC18F87J10 FAMILY
REGISTER 9-9:
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
R/W-0 R/W-0
R-0
R-0
R/W-0 R/W-0
SSP2IE BCL2IE RC2IE TX2IE TMR4IE CCP5IE
bit 7
R/W-0
CCP4IE
R/W-0
CCP3IE
bit 0
bit 7 SSP2IE: Master Synchronous Serial Port 2 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 6 BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module)
1 = Enabled
0 = Disabled
bit 5 RC2IE: EUSART2 Receive Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 4 TX2IE: EUSART2 Transmit Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 3 TMR4IE: TMR4 to PR4 Match Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2 CCP5IE: CCP5 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1 CCP4IE: CCP4 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0 CCP3IE: ECCP3 Interrupt Enable bit
1 = Enabled
0 = Disabled
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
 2005 Microchip Technology Inc.
Advance Information
DS39663A-page 109